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| NTE7069 Integrated Circuit 2 Modulus High Speed Divider w/ECL Output for Phase-Lock Loop (PLL) Synthesized TV Tuner Description: The NTE7069 is an integrated circuit consisting of a 1/128, 1/136 prescaler, high speed frequency divider using an ECL (emitter-coupled logic) circuit configuration in an 8-Lead SIP type package. When the clocks are applied to the pulse swallow control input terminal, M, the dividing ratio is 1/136, and when M is stable ("H" or "L"), the ratio is 1/128. This device operates in the frequency range of 80MHz to 1000MHz. Typical applications for the NTE7069 include prescalers for PLL (Phase Lock Loop) TV tuners and general use in consumer and industrial digital equipment. Features: D High-Speed Operation: fmax = 1GHz D Operates at Low Input Amplitudes: -20dB Min D ECL Level Output: 1.30VP-P Typ Absolute Maximum Ratings: (TA = -20 to +75C unless otherwise specified) Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7V Input Voltage (T, T(REF)), VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC Power Dissipation (TA = +25C), PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.15W Operating Temperature Range, Topr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 to +75C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +125C Recommended Operating Conditions: (TA = -20 to +75C unless otherwise specified) Parameter Supply Voltage Input Amplitude Symbol VCC VIN fIN = 80 to 1000MHz Test Conditions Min 4.5 -20 Typ 5.0 - Max 6.6 4 Unit V dBm Electrical Characteristics: (VCC = 5V 10%, TA = -20 to +75C unless otherwise specified) Parameter Supply Current Input Sensitivity Output Amplitude High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current When the dividing ratio is 1/136 Symbol ICC VIN VO VIH VIL IIH IIL Test Conditions VCC = 5.5V, TA = +25C fIN = 80 to 1000MHz VCC = 4.5V, fIN = 80 to 1000MHz M Terminal, Note 2 VCC = -5V, VIH = 3.5V VCC = -5V, VIL = 1.5V Min - -20 0.9 0.7VCC - - - Typ 33 - 1.3 - - - - Max 50 4 1.7 - 0.3VCC 50 -160 Unit mA dBm VP-P V V A A Note 1. Typical values are at VCC = 5V, TA = +25C. Note 2. Input conditions of pulse swallow control input terminal M: Dividing Ratio 0.7VCC (VIN) When the clocks are applied to M terminal as shown in the left figure, the dividing raito changes from 1/128 to 1/136 Input Conditions Description 1/136 0.5VCC (Vref) 0.3VCC (VIL) 1/128 VIL = 0V, VIN = VCC or VIN = OPEN M terminal is stable at GND or VCC, or opened Pin Connection Diagram (Front View) .768 (19.52) Max .118 (3.0) Max 8 7 6 5 4 3 2 1 N.C. Q (Output) GND GND T (Input) VCC T (REF) M (PSC) .264 (6.72) Max 1 8 .165 (4.2) Min .100 (2.54) Typ .700 (17.78) |
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